Very Large Scale Integrated circuits (IC) have been designed using a variety of tools including netlists, topology of the IC, and schematic databases, where a representation thereof is commonly referred to as a “schematic.” A (design) instance (commonly termed a “layout”) of such an integrated circuit may be generated using the schematic. The layout specifies the location and the individual configuration of each circuit element of the integrated circuit and their interconnections. Typically, the layout is designed to minimize substantially the overall size of the circuit. However, the degree to which the size of circuit elements can be reduced depends strongly on the manufacturing process that is used to manufacture the circuit. Due to the dependency on the manufacturing process, customized layouts may be generated for each manufacturing process that “scale” the circuit to the respective process. As such, the manufacturing process for which a layout was designed is commonly referred to as the “scale” of the circuit/layout.
Similarly, a layout of a circuit may be redesigned (e.g., for the sake of improving the timing, i.e., the maximum operating frequency, of the manufactured circuit). While both the initial layout and the redesigned layout can be designed for the same manufacturing process, the redesigning can comprise changing the size of individual circuit elements. As such, such a redesign may be referred to as “scaling” of a circuit.